1. Field of the Invention
This invention relates generally to a signal recording circuit, and more particularly to a signal limiter circuit for eliminating distortion caused by excessively high level inputs.
2. Description of the Prior Art
In the prior art, when a tape recorder is used for recording a signal, the saturation level of the magnetic tape used therein may give rise to a problem. When the level of an input signal becomes excessively high, the saturation level of the tape may be exceeded with the result that the recording of the input signal is distorted.
For this reason, in the prior art, a so-called AGC circuit, which may adjust or control the gain of an amplifier provided in the recording system in response to the level of an output signal therefrom, is employed so as to make sure that the recording level does not exceed the saturation level.
In this case, however, since the gain of the amplifier is always varied by the AGC circuit in response to the input signal level so as to tend to make the level of the recording signal constant, the dynamic range of the recorded signal is suppressed and hence becomes narrow.
To avoid the above problem associated with the provision of an AGC circuit, a tape recorder has been proposed having a limiter circuit with which, when the input signal level exceeds a reference recording signal level, the input signal to be recorded is limited. In the last mentioned tape recorder, recording is ordinarily carried out in a manner similar to that of manually level-adjust recording, but, when the level of a pulse-like input signal exceeds the reference recording level, the input signal is suppressed or limited, so that the dynamic range for the ordinary recording is as wide as that achieved with manually level-adjusted recording, and the recorded signal is not distorted even if the input signal becomes excessively high.
However, the limiter circuit used in the above mentioned prior art tape recorder is disadvantageous in that it badly affects the signal supplied therefrom to an equalizer circuit and in that it is difficult to select the attack time and recovery time of the limiter circuit.